1. Field of the Invention
The present invention relates to an image data processing apparatus, more particularly relates to an image data processing apparatus characterized by an address generation circuit and an xcex1-blending circuit.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. Especially, along with the recent advances in image data processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel, then pixel data indicating the calculated color is generated and xcex1-blending is performed by using the pixel data. Then, rendering is performed for writing the calculated value of the pixel to an address of a display buffer (frame buffer) corresponding to the pixel.
In the above three-dimensional computer graphics, there are demands for improving the processing speed of the system as a whole by making the xcex1-blending and address generation faster.
An object of the present invention is to provide an image data processing apparatus capable of attaining high speed processing.
To solve the problems of the above related art and to attain the above object, according to a first aspect of the present invention, there is provided an image data processing apparatus, comprising a storage circuit having a plurality of storage areas able to be simultaneously written with a plurality of pixel data and storing a plurality of pixel data indicating colors of a plurality of pixels arranged in a matrix; a plurality of address generation circuits provided corresponding to the plurality of pixel data simultaneously written to the storage areas and generating write addresses as addresses in the storage areas of the storage circuit for writing corresponding pixel data; and a write circuit for writing a plurality of pixel data to the write addresses in the storage areas.
In the image data processing apparatus according to the first aspect of the present invention, the plurality of address generation circuits provided corresponding to the plurality of pixel data to be simultaneously written in the storage circuit generate write addresses, that is, addresses in a storage area of a storage circuit for writing the corresponding pixel data.
The write circuit simultaneously writes the plurality of pixel data at the write address of the storage area of the storage circuit generated in the address generation circuit.
Preferably, the pixel data includes color data indicating the color and a first position data and a second position data respectively indicating a two-dimensional position of a corresponding pixel in the x-direction and y-direction; and the address generation circuit comprises a multiplying circuit for multiplying the second position data with a width data in accordance with a width of the storage area in the x-direction and an adder circuit for generating the write address by adding the first position data and a multiplied result of the multiplying circuit.
More preferably, the pixel data includes color data indicating the color, a first position data and a second position data respectively indicating a two-dimensional position of a corresponding pixel in the x-direction and y-direction and depth data to be used at the time of performing three-dimensional display processing; and the address generation circuit comprises a first multiplying circuit for multiplying the second position data and width data in accordance with a width of the storage area in the x-direction; a first adding circuit for adding the first position data, a multiplied result of the first multiplying circuit, and a first address data for indicating a head address of a predetermined first storage area for storing color data in the storage area to generate the write address of the color data; a second multiplying circuit for multiplying the second position data and the width data; and a second adding circuit for adding the first position data, a multiplied result of the second multiplying circuit, and a second address data for indicating a head address of a predetermined second storage area for storing depth data in the storage area to generate the write address of the depth data.
Preferably, when automatically generating the circuit pattern of at least part of the circuits based on circuit pattern generation data describing at least part of the circuit functions of the image data processing apparatus using a hardware description language, the functions of the multiplying circuit and the adding circuit are written in the same macro cell in the circuit pattern generation data.
According to a second aspect of the invention, there is provided an image data processing apparatus comprising a storage circuit having a plurality of storage areas able to be simultaneously written with the plurality of first pixel data and storing a plurality of first pixel data indicating colors of a plurality of pixels arranged in a matrix; a plurality of pixel data generation circuits provided corresponding to the simultaneously written plurality of first pixel data and each performing color blending using second pixel data and third pixel data for blending a color indicated by the corresponding second pixel data and a color indicated by the third pixel data stored at a write address by a predetermined blending ratio to generate a new color so as to generate first pixel data indicating a new color; and a write circuit for simultaneously writing the plurality of the first pixel data generated to the storage areas of the storage circuit.
In the image data processing apparatus according to the second aspect of the present invention, the plurality of address generation circuits provided corresponding to the plurality of first pixel data to be simultaneously written in the storage circuit uses the second pixel data and the third pixel data for color blending to blend a color indicated by the corresponding second pixel data and a color indicated by third pixel data stored at a write address by a predetermined blending ratio to generate a new color and generates first pixel data indicating the new color.
Then, the write circuit simultaneously writes the plurality of the generated first pixel data in a storage area of the storage circuit.
Preferably, the first pixel data, the second pixel data, and the third pixel data include a plurality of colors and indicate colors by combining values indicated by the plurality of color data and each the pixel data generation circuit comprises a plurality of color data generation circuits provided corresponding to the plurality of color data and each performing color blending using the corresponding color data of the second pixel data and the third pixel data for blending a color indicated by the corresponding color data of the corresponding second pixel data and a color indicated by the corresponding color data of the third pixel data stored at the write address by a predetermined blending ratio to generate a new color and thereby generate the corresponding color data of the first pixel data indicating the new color.
More preferably, the pixel data generation circuit comprises a subtracting circuit for subtraction using the corresponding color data of the second pixel data and the corresponding color data of the third pixel data and a multiplying circuit for multiplying a subtracted result of the subtracting circuit with blending ratio data indicating the blending ratio.
Preferably, the pixel data generation circuit further comprises an adding circuit for adding a multiplied result of the multiplying circuit and dither data.
Preferably, when automatically generating the circuit pattern of at least part of the circuits based on circuit pattern generation data describing at least part of the circuit functions of the image data processing apparatus using a hardware description language, the functions of the subtracting circuit and the multiplying circuit of the pixel data generation circuit are written in the same macro cell in the circuit pattern generation data.
Preferably, when automatically generating the circuit pattern of at least part of the circuits based on circuit pattern generation data describing at least part of the circuit functions of the image data processing apparatus using a hardware description language, the functions of the plurality of color data generation circuits are written in the same macro cell in the circuit pattern generation data.
According to a third aspect of the present invention, there is provided an image data processing apparatus for defining a three-dimensional model by combining a plurality of unit graphics and generating pixel data indicating a color for each pixel arranged in a matrix in a display device, comprising a polygon rendering data generation circuit for generating polygon rendering data including R (red), G (green), and B (blue) data for vertexes of the unit graphics; a data interpolation circuit for interpolating the polygon rendering data of vertexes of the unit graphics to generate pixel data of pixel positions inside the unit graphics; a storage circuit having a plurality of storage areas able to be simultaneously written with the R, G, B data of a plurality of the pixel data and storing display data including the R, G, B data of a plurality of the pixel data; a plurality of address generation circuits provided corresponding to the plurality of the pixel data to be simultaneously written to the storage areas and each generating a write address as an address in the storage areas of the storage circuit for being written with the R, G, B data of the corresponding pixel data; and a write circuit for writing the R, G, B data of a plurality of the pixel data to the write addresses in the storage areas.
According to a fourth aspect of the present invention, there is provided an image data processing apparatus for defining a three-dimensional model by combining a plurality of unit graphics and generating pixel data indicating a color for each pixel arranged in a matrix in a display device, comprising a polygon rendering data generation circuit for generating polygon rendering data including R (red), G (green), and B (blue) data of each vertex for vertexes of the unit graphics; a data interpolation circuit for interpolating the polygon rendering data of vertexes of the unit graphics to generate first pixel data of pixel positions inside the unit graphics; a storage circuit having a plurality of storage areas able to be simultaneously written with a plurality of the second pixel data and storing display data including a plurality of second pixel data; pixel data generation circuits provided corresponding to the simultaneously written plurality of the second pixel data and each performing color blending using the first pixel data and the third pixel data for blending a color indicated by the first pixel data and a color indicated by third pixel data stored in a write address by a predetermined blending ratio to generate a new color so as to generate the second pixel data indicating the new color; and a write circuit for simultaneously writing a plurality of the generated second pixel data to the storage areas of the storage circuit.